View PSMN3R5-30LL_4740589.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

D
D
D
D
D R A
R
R
R
R A
A
A
A
PSMN3R5-30LL
Rev. 01 -- 18 February 2010
FT
FT
FT
FT D R R A FT D R A FT D A
N-channel 30 V 3.6 m logic level MOSFET
FT D
D R A FT D R A FT D R A A FT D R D FT
Objective data sheet
FT
D R A FT D R A FT D R A F D R
1. Product profile
1.1 General description
R
Logic level N-channel MOSFET in QFN3333 package qualified to 150 C. This product is designed and qualified for use in a wide range of industrial, communications and power supply equipment.
R A FT D R
A FT D A FT D R A
1.2 Features and benefits
High efficiency due to low switching and conduction losses Small footprint for compact designs Suitable for logic level gate drive sources
1.3 Applications
Battery protection DC-to-DC converters Load switching Power ORing
1.4 Quick reference data
Table 1. VDS ID Ptot Tj Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1 Tmb = 25 C; see Figure 2 Min -55 VGS = 10 V; Tj(init) = 25 C; ID = 40 A; Vsup 30 V; unclamped; RGS = 50 VGS = 10 V; ID = 15 A; VDS = 15 V; see Figure 13 and 14 VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 12 Typ Max 30 40 71 150 118 Unit V A W C mJ drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation junction temperature Symbol Parameter
Avalanche ruggedness EDS(AL)S non-repetitive drain-source avalanche energy Dynamic characteristics QGD QG(tot) gate-drain charge total gate charge 5.2 37 nC nC
Static characteristics RDSon drain-source on-state resistance 3 5 3.6 m m
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
2. Pinning information
Table 2. Pin 1 2 3 4 5,6,7,8 S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain
8765
D
D
D R A FT D
R A FT D R A FT
R A F R A FT
Simplified outline
Graphic symbol
D
D
D R A FT D
R A
G
mbb076
S
1234 Transparent top view
SOT873-1 (HVSON8)
3. Ordering information
Table 3. Ordering information Package Name PSMN3R5-30LL HVSON8 Description plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3.3 x 3.3 x 0.85 mm Version SOT873-1 Type number
4. Limiting values
Table 4. Symbol VDS VDGR VGS ID IDM Ptot Tstg Tj Tsld(M) Limiting values Parameter drain-source voltage drain-gate voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature peak soldering temperature source current peak source current Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1 tp 10 s; pulsed; Tmb = 25 C Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 150 C Tj 150 C; Tj 25 C; RGS = 20 k Min -20 -55 -55 Max 30 30 20 40 40 423 71 150 150 260 Unit V V V A A A W C C C
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode IS ISM EDS(AL)S 40 423 118 A A mJ
Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 40 A; Vsup 30 V; drain-source avalanche unclamped; RGS = 50 energy
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
2 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R D
FT
D
D
03aa16
R
R
R A
A FT
A
120 ID (A) 100
003a a e 139
F
FT
120 Pder (%) 80
D
D R A FT D
R A FT D A FT R
80
D R A
60
40
(1)
40
20
0 0 50 100 150 200 Tmb (C)
0 0 50 100 150 Tmb (C) 200
Fig 1.
Continuous drain current as a function of mounting base temperature
Fig 2.
Normalized total power dissipation as a function of mounting base temperature
5. Thermal characteristics
Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ 0.9 [tbd] Max 1.77 Unit K/W K/W thermal resistance from see Figure 3 junction to mounting base
1 Zth (j-mb)
003a a e 141
(K/W)
= 0.5
0.2 10-1 0.1 0.05 0.02 tp single shot 10-2 10-6 10-5 10-4 10-3 10-2 10-1 T tp (s) 1 t P = tp T
Fig 3.
Transient thermal impedance from junction to mounting base as a function of pulse duration; typical values
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
3 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
6. Characteristics
Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 0.25 mA; VGS = 0 V; Tj = -55 C ID = 0.25 mA; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 9 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 9 and 10 ID = 1 mA; VDS = VGS; Tj = -55 C; see Figure 9 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VDS = 30 V; VGS = 0 V; Tj = 125 C VGS = 20 V; VDS = 0 V; Tj = 25 C VGS = -20 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 15 A; Tj = 100 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 150 C; see Figure 11 VGS = 10 V; ID = 15 A; Tj = 25 C; see Figure 12 RG internal gate resistance f = 1 MHz (AC) total gate charge ID = 15 A; VDS = 15 V; VGS = 10 V; see Figure 13 and 14 ID = 0 A; VDS = 0 V; VGS = 10 V QGS QGS(th) QGS(th-pl) QGD VGS(pl) Ciss Coss Crss gate-source charge pre-threshold gate-source charge post-threshold gate-source charge gate-drain charge gate-source plateau voltage input capacitance output capacitance reverse transfer capacitance ID = 15 A; VDS = 15 V; VGS = 10 V; see Figure 13 and 14 VDS = 15 V; see Figure 13 and 14 VDS = 15 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 15 ID = 15 A; VDS = 15 V; VGS = 10 V; see Figure 13 and 14 ID = 15 A; VDS = 15 V; VGS = 10 V; see Figure 13 Min 27 30 0.65 1.3 Typ 1.7 0.04 10 10 5.2 3 2.4
D
D
Max 2.15 2.45 2 50 100 100 5 6.4 3.6 -
D R A FT D
R A FT D R
Unit V V V V V A A nA nA m m m
R A F R A FT
A FT D R
D
Static characteristics
A FT D R A
Dynamic characteristics QG(tot) 37 33 5.9 3.4 2.5 5.2 2.7 2061 409 177 nC nC nC nC nC nC V pF pF pF
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
4 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
Table 6. Symbol td(on) tr td(off) tf VSD trr Qr
Characteristics ...continued Parameter turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time recovered charge IS = 15 A; VGS = 0 V; Tj = 25 C; see Figure 16 IS = 15 A; dIS/dt = 100 A/s; VGS = 0 V; VDS = 15 V Conditions VDS = 15 V; RL = 1 ; VGS = 4.5 V; RG(ext) = 4.7 ; Tj = 25 C Min Typ 23 54 35 18 0.85 34 34
D
D
Max 1.2 -
D R A FT D
Unit ns
R A FT D R
ns ns ns V ns nC
R A F R A FT D
A FT D R A
FT D R A
Source-drain diode
100 gfs (S) 80
003aae144
50 ID (A) 40
003aae143
60
30
40
20 Tj = 175 C Tj = 25 C
20
10
0 0 10 20 30 40 I D (A) 50
0 0 1 2 3 VGS (V) 4
Fig 4.
Forward transconductance as a function of drain current; typical values
Fig 5.
Transfer characteristics: drain current as a function of gate-source voltage; typical values
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
5 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R D
FT
D
D R A
R A
R A
4000
C (pF)
003a a e 145
25 RDSon (m) 20
003aae148
FT D
F
FT D
Ciss
R
R A FT D
A FT D
3000
Crss
R A FT D
15
R A
2000 10 1000 5
0 0 2.5 5 7.5
VGS (V)
10
0 0 4 8 12 16 20 VGS (V)
Fig 6.
Input and reverse transfer capacitances as a function of gate-source voltage; typical values
50
003aae142
Fig 7.
Drain-source on-state resistance as a function of gate-source voltage; typical values
003a a c337
ID (A) 40
10 4.5 3.5 3
3 VGS (th) (V) 2 max typ min 1
30 2.8 20 2.6 10 VGS (V) = 2.4 0 0 0.25 0.5 0.75 VDS(V) 1
0 -60
0
60
120
Tj (C)
180
Fig 8.
Output characteristics: drain current as a function of drain-source voltage; typical values
Fig 9.
Gate-source threshold voltage as a function of junction temperature
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
6 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R D
FT
D
D R A
R A
R A
10-1 ID (A) 10-2 min 10-3 typ
003aab271
3.2 a 2.4
003aad774
FT D R R A FT D R A FT A
F
FT D
FT D
max
D R A
1.6
10
-4
10-5
0.8
10-6 0 1 2 VGS (V) 3
0 -60
0
60
120
Tj (C)
180
Fig 10. Sub-threshold drain current as a function of gate-source voltage
Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature
20
RDSon (m)
003a a e 147
VDS ID
15
VGS (V) = 3 VGS(pl) VGS(th) VGS 3.5 QGS1 QGS2 QGD QG(tot)
003aaa508
10
5
4.5
10
QGS
0 0 10 20 30
ID (A)
40
Fig 13. Gate charge waveform definitions
Fig 12. Drain-source on-state resistance as a function of drain current; typical values
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
7 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
10 VGS (V) 8
15 V
003a a e 149
104 C (pF)
003a a e 146
A
A
A FT D R D
FT
D
D R A FT D
Ciss 6V
R A FT D R A FT D R A
R A F R A FT D FT D
6
103 VDS = 24 V
R A
4
Coss
2
Crss
0 0 10 20 30
QG (nC)
40
102 10-1
1
10
VDS (V)
102
Fig 14. Gate-source voltage as a function of gate charge; typical values
Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values
003aae150
50 IS (A) 40
30
20 Tj = 175 C 10 Tj = 25 C
0 0 0.3 0.6 0.9 VSD (V) 1.2
Fig 16. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
8 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
7. Package outline
HVSON8: plastic thermal enhanced very thin small outline package; no leads; 8 terminals; body 3.3 x 3.3 x 0.85 mm
D
D
D R A FT D
R A FT D
SOT873-1
R A F R
R A FT D R
A FT D A FT D R A
X D B A
terminal 1 index area
E
A
A1 c detail X
terminal 1 index area e
1
e1 b
4
C v w
M M
CAB C
y1 C
y
L1
Eh
L2
8 5
Dh 0 1 scale DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 b c 0.2 D 3.4 3.2 Dh 2.3 2.2 E 3.4 3.2 Eh e e1 L1 L2 v 0.1 w 0.05 y 0.1 y1 0.1 2 mm
0.05 0.35 0.00 0.25
0.55 0.52 1.68 0.65 1.95 0.45 0.42 1.58 REFERENCES
OUTLINE VERSION SOT873-1
IEC ---
JEDEC ---
JEITA ---
EUROPEAN PROJECTION
ISSUE DATE 05-06-16 05-06-21
Fig 17. Package outline SOT873-1 (HVSON8)
PSMN3R5-30LL_1 All information provided in this document is subject to legal disclaimers. (c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
9 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
8. Revision history
Table 7. Revision history Release date 20100218 Data sheet status Objective data sheet Change notice Document ID PSMN3R5-30LL_1
D
D
Supersedes -
D R A FT D
R A FT D R A FT D R A
R A F R A FT D FT D R A
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
10 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
9. Legal information
9.1 Data sheet status
Product status[3] Development Qualification Production Definition
D
D
D R A FT D
R A FT D R A FT D R
R A F R A FT D
Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
A FT D R
This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
A
Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer's third party customer(s) (hereinafter both referred to as "Application"). It is customer's sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.3
Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
11 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products -- Unless the data sheet of an NXP Semiconductors product expressly states that the product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever
customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications.
D
D
D
R
R
R
A
A
A
FT D R A R A FT
F
FT
D
R
A
FT D
FT
D
9.4
Trademarks
D R A
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PSMN3R5-30LL_1
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Objective data sheet
Rev. 01 -- 18 February 2010
12 of 13
D
D
D
D
NXP Semiconductors
PSMN3R5-30LL
FT FT FT
N-channel 30 V 3.6 m logic level MOSFET
FT FT FT D D D R R R A A A FT FT
D R A FT D
R
R
R
R A D R R A
A
A
A FT
D
D R
R
A
A
A FT D R
FT
11. Contents
1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Contact information. . . . . . . . . . . . . . . . . . . . . .12
D
D
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
D R A FT D
R A FT D R A FT D R A
R A F R A FT D FT D R A
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 18 February 2010 Document identifier: PSMN3R5-30LL_1

▲Up To Search▲

Price & Availability of PSMN3R5-30LL

	To Download PSMN3R5-30LL Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .